For ultra large scale integrated (ULSI) circuits application, one of the features is to shrink the dimensions of devices down to sub-micron or deep sub-micron range. In NMOS, a channel region in the semiconductor under the gate is doped with ions that are opposite to that of the source and drain. The operation of the MOS includes the application of applying a voltage to the gate. By varying the transverse electrical field, it is possible to control the current flow by modulating the longitudinal conductance of the channel. If the drain bias is applied such that source-body and drain-body junctions remain reverse-bias. A positive bias is applied to the gate of the NMOS, electrons will be attracted to the channel region, once enough electrons are drawn into the channel region by the positive gate voltage, the channel connects the source and the drain.
One type of the NMOS is called a high voltage NMOS (HVNMOS), which can be operated under applying a high operation voltage. FIG. 1 shows a prior art high voltage NMOS (HVNMOS). A P-well and an N-well are respectively formed on a P type dopant epitaxial silicon layer formed on a wafer or substrate. The N-well region plays the role of drain in the structure. Field oxide regions 2 are formed on the N-well to reduce the electric field near the drain. A gate oxide 4 is formed on the surface of the both wells and adjacent to the field oxide 2. A gate 6, typically composed of polysilicon, is formed on the gate oxide. A drain contact 8 is formed in the N-well by doping impurities into a desired region of the well. In general, the dopant concentration of the drain contact 8 is higher than that of the N-well. The source 10 is formed in the P-well adjacent to the gate, typically the source 10 is created by conventional ion implantation. An isolation layer 12 is deposited on the gate 6 and a portion of the dual well to expose a portion of the source 10 and the drain 8. The channel region of the HVNMOS is located within the P-well under the gate oxide 4.
The MOS is a four-terminal device, a contact can also be made to the body region. A bias can also be applied between the source and body and such a bias will have an impact on threshold voltage (Vt). The impact of the source-body bias on Vt is referred to the body effect. Unfortunately, in the structure of the aforesaid HVNMOS, the P-well is directly short circuit to the P-substrate. Thus, the aforementioned HVNMOS suffers the issue of the body effect arisen by the P-substrate short to the source. Further, the device can not allow negative voltage operation.
What is needed in the art is a method to form a HVMOS in an epitaxial layer and semiconductor substrate which has a high breakdown voltage and to eliminate the body effect induced by the P-substrate.